In order to track chip, wafer, and lot identification (ID), e-fuses (silicided polysilicon PC) or laser-fuses can be blown into each module. Blowing the fuses, however, takes time and adds cost during wafer testing. For example, blowing fuses can take 0.75 s per PS3 cell processor.
It is also known to use random differential Idsat (high drain or saturation current) output of paired MOSFET transistors to generate a unique binary chip ID. In this case, a unique differential Idsat is stored for future reference and for chip identification. Comparator circuitry is typically used to read chip ID. For example, 16×16 arrays of paired MOSFET's are used (256 MOSFET pairs) to uniquely identify a chip running in a “high volume” manufacturing fabrication. Advantages of this technique include the elimination e-fuse or laser fuse blow test time and the possible elimination of tampering with ECID (passports, smartchips, etc.).
This latter technique has disadvantages, however. For example, measuring MOSFET Idsat requires correct biasing of the FET S/D/G and the repeatable application of test voltage, currents, and temperature since the measured differential Idsat will be a function of the test conditions. Another disadvantage relates to how the MOSFET Idsat and other electrical properties change over time due to (a) charge injection into the gate dielectric, (b) radiation (alpha particles, etc.), (c) mobile ions, and (d) wear out of the gate dielectric (trap creation), etc. Another disadvantage relates to how the electro static discharge (ESD) destructive event (blowing the MOSFET gates) can eliminate electronic chip identification (ECID) capability.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.